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ARCHITECTURE OVERVIEW

A complete Block Diagram of the CCD Digital Reference Evaluation Board is shown in .

MASTER CLOCK

The Master Clock runs at eight times the Pixel clock frequency. The maximum pixel clock frequency is 6 MHz, which yields

a maximum system clock frequency of 48 MHz. For slower Pixel clock frequencies, decrease the master clock frequency.

The Default setting of the evaluation board is a 40 MHz system clock, with a pixel clock frequency of 5 MHz.

The KAF-4301E is an exception to this. It provides pixel frequencies of 2.5MHz and 1.25 MHz by dividing the 40MHz master

clock by 16 and 32. The pixel frequency is selected using SW2. This is an 8-position switch that usually selects a CCD

binning mode (see section Binning Modes). The KAF-4301E timing program does not support binning at this time and,

instead, uses this switch to select the pixel rate (see Table 5: KAF-4301E SW2 Pixel Rate Settings). The pixel rate is 1.25

MHz when SW2 is set to position 0 and 2.5 MHz when set in any other position.

PLD1

PLD1 contains the Clocking State Machine that controls the operational flow of the evaluation board (Figure 2: Clocking

State Machine). PLD1 generates the CCD clock timing, A/D converter timing and frame grabber sync signals. The PLD1

controls the image line and frame length [dependent upon the CCD switch settings], as well as the horizontal and vertical

CCD clock timing [dependent upon the binning mode BIN switch settings.]

PLD2

PLD2 controls the integration timing, which is dependent upon the INT switch settings. PLD2 also programs the AD9816’s

registers to a default condition upon power up via a three wire serial interface. Additionally, if the user chooses to adjust

the AD9816’s register settings, the PLD2 controls the programming of these registers.

CCD CLOCK DRIVERS

Elantec clock drivers, designed to drive the large capacitance loads presented by the clock gates of the CCD, are used to

generate the horizontal and vertical clocks. The Elantec drivers accept TTL inputs, and level shift to the required peak-to-

peak voltage swing of the CCD clocks. The peak-to-peak swing of the clocks is adjustable. The outputs of the drivers are

AC coupled, providing adjustable offset of the clocks from the negative rail to the positive rail. Using a separate IC for each

vertical clock (V1,V2), a maximum 4 amp output drive current per vertical clock channel is available. A single IC is used to

drive H1, and H2, giving a maximum 2A output drive current per Horizontal clock channel.

The reset clock driver utilizes two fast switching transistors, designed for a fast switching input signal with a narrow pulse

width. The peak-to-peak voltage swing and the offset voltage are adjustable.

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MTD PS Spezifikationen Seite 7